The present invention relates to a delayed locked loop, and more particularly, to a delayed locked loop circuit with duty cycle correction and a method of controlling the same.
In general, clocks that are used in systems or circuits are used as references to match operating timings. The clocks may also be used to ensure a high-speed operation without the occurrence of any error. When a clock that is input from the outside of a semiconductor circuit is used in the semiconductor circuit, clock skew, that is, a time delay occurs due to an internal circuit. A delay locked loop circuit is used to correct the time delay, such that an internal clock and the external clock have the same phases as each other.
Further, when the semiconductor circuit operates, the clocks need to be delay locked. However, it is also important to maintain a duty ratio of a rising period and a falling period of each of the clocks to 50:50. Therefore, general delay locked loop circuits to which duty cycle correction circuits are added are being currently used in semiconductor circuit technology.
Meanwhile, the delay locked loop circuit with duty cycle correction according to the related art may cause a duty correction error according to a change in process, voltage, and temperature (hereinafter, simply referred to as “PVT”).
That is, after a rising clock RCLK in synchronization with a rising edge of the external clock and a falling clock FCLK in synchronization with a falling edge of the external clock are delay locked, a phase delay may occur due to the change in PVT.
The duty correction is performed by comparing a phase of the rising clock RCLK with a phase of the falling clock FCLK and adjusting the width of a rising period or a falling period of each of the two clocks. When the amount of phase delay of the rising clock RCLK is different from that of the falling clock FCLK, the phase of the rising clock RCLK is not corrected. FIG. 1 is a diagram illustrating an early stage in which a duty correction error occurs. As in a duty cycle corrected clock DCC_OUT as shown in FIG. 1A, an error occurs when the duty ratio of the rising period and the falling period is not 50:50.
The duty cycle corrected clock DCC_OUT is fed back to the delay locked loop circuit and subjected to delay locked signal processing. Then, in the duty cycle correction circuit, the processed duty cycle corrected clock DCC_OUT is subjected to the duty cycle correction. These operations are repeatedly performed.
Since the delay locked signal processing operation and the duty cycle correction are repeated, the skew occurring when the duty correction error occurs, that is, a phase distortion component is accumulated. As a result, as in FIG. 1B, an abnormal signal in which a high-level period and a low-level period are not normally repeated is output.
As described above, the delay locked loop circuit with duty cycle correction according to the related art causes a duty cycle correction error due to a phase delay occurring according to a change in PVT. This causes a failure in the operation of the semiconductor circuit that uses the delay locked loop circuit.